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ISL6745A
Data Sheet September 11, 2008 FN6703.1
Improved Bridge Controller with Precision Dead Time Control
The ISL6745A is a low-cost double-ended voltage-mode PWM controller designed for half-bridge and full-bridge power supplies and line-regulated bus converters. It provides precise control of switching frequency, adjustable soft-start, and overcurrent shutdown. In addition, the ISL6745A allows for accurate adjustment of MOSFET non-overlap time ("deadtime") with deadtimes as low as 35ns, allowing power engineers to optimize the efficiency of open-loop bus converters. The ISL6745A also includes a control voltage input for closed-loop PWM and line voltage feed-forward functions. The ISL6745A is identical to the ISL6745, but is optimized for higher noise environments. Low start-up and operating currents allow for easy biasing in both AC/DC and DC/DC applications. This advanced BiCMOS design also features adjustable switching frequency up to 1MHz, 1A FET drivers, and very low propagation delays for a fast response to overcurrent faults. The ISL6745A is available in a space-saving MSOP-10 package and is guaranteed to meet rated specifications over a wide -40C to +105C temperature range.
Features
* Precision Duty Cycle and Deadtime Control * 100A Start-up Current * Adjustable Delayed Overcurrent Shutdown and Re-Start * Adjustable Oscillator Frequency Up to 2MHz * 1A MOSFET Gate Drivers * Adjustable Soft-Start * Internal Over-Temperature Protection * 35ns Control to Output Propagation Delay * Small Size and Minimal External Component Count * Input Undervoltage Protection * Pb-Free (RoHS Compliant)
Applications
* Half-bridge Converters * Full-bridge Converters * Line-regulated Bus Converters * AC/DC Power Supplies * Telecom, Datacom, and File Server Power
Ordering Information
PART NUMBER (Note) PART MARKING TEMP. RANGE (C) PACKAGE (Pb-Free) PKG. DWG. #
Pinout
ISL6745A (10 LD MSOP) TOP VIEW
SS 1 RTD 2 VERR 3 CS 4 CT 5 10 VDD 9 VDDP 8 OUTB 7 OUTA 6 GND
ISL6745AAUZ* 6745A
-40 to +105 10 Ld MSOP M10.118
*Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
Internal Architecture
FL VBIAS Q + BG UVLO T Q PWM TOGGLE
VDDP
VDD
VBIAS 5.00V
OUTA
OUTB VBIAS 70A ON
INTERNAL OT SHUTDOWN 130C - 150C
I DCH= 55 x IRTD
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FN6703.1 September 11, 2008
GND
SS VBIAS SS CLAMP RTD IRTD 2.0V + 4.0V VBIAS 160A ON 2.8V + PEAK SQ RQ + VALLEY RESET DOMINANT CLK SQ + SS CHARGED + 3.9V 15A
ISL6745A
RQ OC LATCH
CT 0.8V
Q Q 50s RETRIGGERABLE ONE SHOT SS LOW + 0.27V
FAULT LATCH SS SET DOMINANT SQ RQ VBIAS VBIAS UV 4.65V 4.80V + BG FL
SQ IDCH RQ ON PWM LATCH SET DOMINANT
CS 0.6V
+ -
OC DETECT
PWM COMPARATOR VBIA
S
CT 15A
+ -
VERR 0.8 0.8
SS
Typical Application - Telecom DC/DC Converter
VIN+ Q1 + VOUT CR1
+
C1
T1
3
36V TO 75V (100V Max.) T2 Q2 C2 CR2 L1 VINCR3 CR4 U2 ISL2100A
1 VDD 2 HB LO 8 VSS 7 LI 6 HI 5
C10 RETURN
ISL6745A
C6
3 HO 4 HS
R1 U1 ISL6745A
1 SS VDD 10
C9 R6 R10 R7 C8
R11
U3
2 RTD VDDP 9 3 VERR OUTB 8
Q3
4 CS 5 CT
OUTA 7 GND 6
R4
C7
R8
R3 VR1 C2 R2 C3 C4 C5 VR2 R5 U4 TL431 R9
FN6703.1 September 11, 2008
ISL6745A
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V OUTA, OUTB . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5V Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) 10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Maximum Junction Temperature . . . . . . . . . . . . . . .-55C to +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +105C Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 9V to 16V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are to be measured with respect to GND, unless otherwise specified.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram on page 2 and Typical Application schematic on page 3. 9V < VDD < 16V, RTD = 51.1k, CT = 470pF, TA = -40C to +105C, Typical values are at TA = +25C; Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SUPPLY VOLTAGE Start-Up Current, IDD Operating Current, IDD UVLO START Threshold UVLO STOP Threshold Hysteresis CURRENT SENSE Current Limit Threshold CS to OUT Delay CS Sink Current Input Bias Current PULSE WIDTH MODULATOR Minimum Duty Cycle Maximum Duty Cycle
VDD< START Threshold COUTA,B = 1nF
5.9 5.3 -
5 6.3 5.7 0.6
175 8.5 6.6 6.3 -
A mA V V V
0.55 (Note 3) 8 -1
0.6 35 10 -
0.65 1
V ns mA A
VERROR < CT Offset CT = 470pF, RTD = 51.1k CT = 470pF, RTD = 1.1k (Note 3)
-
94 99 0.8 1 0.8
0 -
% % % V/V V/V V/V
VERR to PWM Comparator Input Gain CT to PWM Comparator Input Gain SS to PWM Comparator Input Gain OSCILLATOR Charge Current RTD Voltage Discharge Current Gain CT Valley Voltage CT Peak Voltage TA = +25C (Note 3) (Note 3)
-
143 1.925 45 0.75 2.70
156 2 0.8 2.80
170 2.075 65 0.85 2.90
A V A/A V V
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FN6703.1 September 11, 2008
ISL6745A
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram on page 2 and Typical Application schematic on page 3. 9V < VDD < 16V, RTD = 51.1k, CT = 470pF, TA = -40C to +105C, Typical values are at TA = +25C; Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SOFT-START Net Charging Current SS Clamp Voltage Overcurrent Shutdown Threshold Voltage Overcurrent Discharge Current Reset Threshold Voltage OUTPUT High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Rise Time Fall Time THERMAL PROTECTION Thermal Shutdown Thermal Shutdown Clear Hysteresis, Internal Protection NOTES:
45 3.8 (Note 3) 12 0.25
4.0 3.9 15 0.27
68 4.2 23 0.31
A V V A V
VDD - VOUTA or VOUTB, IOUT = -100mA IOUT = 100mA CGATE = 1nF, VDD = 12V CGATE = 1nF, VDD = 12V
-
0.5 0.5 17 20
2.0 1.0 60 60
V V ns ns
(Note 3) (Note 3) (Note 3)
-
145 130 15
-
C C C
3. Limits established by characterization and are not production tested.
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FN6703.1 September 11, 2008
ISL6745A Typical Performance Curves
65 CT DISCHARGE CURRENT GAIN 1-104
60 1-103
CT = 1000pF DEADTIME (ns) CT = 680pF CT = 470pF
55
CT = 270pF CT = 100pF
50
100
45
40 0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
10
10
20
30
40
RTD CURRENT (mA)
50 60 RTD (k)
70
80
90
100
FIGURE 1. OSCILLATOR CT DISCHARGE CURRENT GAIN
FIGURE 2. DEADTIME vs CAPACITANCE
600 NORMALIZED CHARGING CURRENT OSCILLATOR FREQUENCY (kHz)
1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 0.95 -40 -25 -10 5 20 35 50 65 80 95 110
500
400
300
200
100 0 100
200
300
400
500 600 CT (pF)
700
800
900
1k
TEMPERATURE (C)
FIGURE 3. CAPACITANCE vs OSCILLATOR FREQUENCY (RTD = 49.9k)
FIGURE 4. CHARGE CURRENT vs TEMPERATURE
1.07 1.06 NORMALIZED VOLTAGE 1.05 1.04 1.03 1.02 1.01 1.00 0.99 0.98 0 10 20 30 40 50 RTD (k) 60 70 80 90 100
FIGURE 5. TIMING CAPACITOR VOLTAGE vs RTD
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FN6703.1 September 11, 2008
ISL6745A Pin Descriptions
VDD - VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. The total supply current, IDD, will be dependent on the load applied to outputs OUTA and OUTB. Total IDD current is the sum of the quiescent current and the average output current. Knowing the operating frequency, FSW, and the output loading capacitance charge, Q, per output, the average output current can be calculated from Equation 1:
I OUT = 2 * Q * F SW A (EQ. 1)
during start-up, controls the overcurrent shutdown delay, and the overcurrent and short circuit hiccup restart period. VERR - The inverting input of the PWM comparator. The error voltage is applied to this pin to control the duty cycle. Increasing the signal level increases the duty cycle. The node may be driven with an external error amplifier or an opto-coupler. VDDP - VDDP is the separate collector supply to the gate drive. Having a separate VDDP pin helps isolate the analog circuitry from the high power gate drive noise.
Functional Description
Features
The ISL6745A PWM is an excellent choice for low cost bridge topologies for applications requiring accurate frequency and deadtime control. Among its many features are 1A FET drivers, adjustable soft-start, overcurrent protection and internal thermal protection, allowing a highly flexible design with minimal external components.
RTD - This is the oscillator timing capacitor discharge current control pin. A resistor is connected between this pin and GND. The current flowing through the resistor determines the magnitude of the discharge current. The discharge current is nominally 55x this current. The PWM deadtime is determined by the timing capacitor discharge duration. CT - The oscillator timing capacitor is connected between this pin and GND. CS - This is the input to the overcurrent protection comparator. The overcurrent comparator threshold is set at 0.600V nominal. The CS pin is shorted to GND at the end of each switching cycle. Depending on the current sensing source impedance, a series input resistor may be required due to the delay between the internal clock and the external power switch. Exceeding the overcurrent threshold will start a delayed shutdown sequence. Once an overcurrent condition is detected, the soft-start charge current source is disabled. The soft-start capacitor begins discharging through a 15A current source, and if it discharges to less than 3.9V (Sustained Overcurrent Threshold), a shutdown condition occurs and the OUTA and OUTB outputs are forced low. When the soft-start voltage reaches 0.27V (Reset Threshold) a soft-start cycle begins. If the overcurrent condition ceases, and then an additional 50s period elapses before the shutdown threshold is reached, no shutdown occurs. The SS charging current is re-enabled and the soft-start voltage is allowed to recover. GND - Reference and power ground for all functions on this device. Due to high peak currents and high frequency operation, a low impedance layout is necessary. Ground planes and short traces are highly recommended. OUTA and OUTB - Alternate half cycle output stages. Each output is capable of 1A peak currents for driving power MOSFETs or MOSFET drivers. Each output provides very low impedance to overshoot and undershoot. SS - Connect the soft-start timing capacitor between this pin and GND to control the duration of soft-start. The value of the capacitor determines the rate of increase of the duty cycle
Oscillator
The ISL6745A has an oscillator with a frequency range to 2MHz, programmable using a resistor RTD and capacitor CT. The switching period may be considered to be the sum of the timing capacitor charge and discharge durations. The charge duration is determined by CT and the internal current source (assumed to be 160A in the formula). The discharge duration is determined by RTD and CT.
T C 1.25 x10 * C T
4
s s
(EQ. 2) (EQ. 3)
1 T D ---------------------------------------------------------------------------- * R TD * C T CTDisch arg eCurrentGain 1 T OSC = T C + T D = --------------F OSC s
(EQ. 4)
where TC and TD are the approximate charge and discharge times, respectively, TOSC is the oscillator free running period, and FOSC is the oscillator frequency. One output switching cycle requires two oscillator cycles. The actual times will be slightly longer than calculated due to internal propagation delays of approximately 5ns/transition. This delay adds directly to the switching duration, and also causes overshoot of the timing capacitor peak and valley voltage thresholds, effectively increasing the peak-to-peak voltage on the timing capacitor. Additionally, if very low charge and discharge currents are used, there will be an increased error due to the input impedance at the CT pin. The above formulae help with the estimation of the frequency. Practically, effects like stray capacitances that affect the overall CT capacitance, variation in RTD voltage and charge current over-temperature, etc. exist, and are best evaluated in-circuit. Equation 2 follows from the basic dV capacitor current equation, i = C x . In this case, with
dt
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FN6703.1 September 11, 2008
ISL6745A
variation in dV with RTD (Figure 5), and in charge current (Figure 4), results from Equation 2 would differ from the calculated frequency. The typical performance curves may be used as a tool along with the previous equations as a more accurate tool to estimate the operating frequency more accurately. The maximum duty cycle, D, and deadtime, DT, can be calculated from:
D = T C T OSC DT = ( 1 - D ) T OSC s (EQ. 5) (EQ. 6)
Overcurrent Operation
Overcurrent delayed shutdown is enabled once the soft-start cycle is complete. If an overcurrent condition is detected, the soft-start charging current source is disabled and the soft-start capacitor is allowed to discharge through a 15A source. At the same time a 50s retriggerable one-shot timer is activated. It remains active for 50s after the overcurrent condition ceases. If the soft-start capacitor discharges to 3.9V, the output is disabled. This state continues until the soft-start voltage reaches 270mV, at which time a new soft-start cycle is initiated. If the overcurrent condition stops at least 50s prior to the soft-start voltage reaching 3.9V, the soft-start charging currents revert to normal operation and the soft-start voltage is allowed to recover.
Soft-Start Operation
The ISL6745A features a soft-start using an external capacitor in conjunction with an internal current source. Soft-start reduces stresses and surge currents during start-up. The oscillator capacitor signal, CT, is compared to the soft-start voltage, SS, in the SS comparator which drives the PWM latch. While the SS voltage is less than 3.5V, duty cycle is limited. The output pulse width increases as the soft-start capacitor voltage increases up to 3.5V. This has the effect of increasing the duty cycle from zero to the maximum pulse width during the soft-start period. When the soft-start voltage exceeds 3.5V, soft-start is completed. Soft-start occurs during start-up and after recovery from an overcurrent shutdown. The soft-start voltage is clamped to 4V.
Thermal Protection
An internal temperature sensor protects the device should the junction temperature exceed +145C. There is approximately +15C of hysteresis.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. VDD should be bypassed directly to GND with good high frequency capacitance.
Gate Drive
The ISL6745A is capable of sourcing and sinking 1A peak current, and may also be used in conjunction with a MOSFET driver such as the ISL6700 for level shifting. To limit the peak current through the IC, an external resistor may be placed between the totem-pole output of the IC (OUTA or OUTB pin) and the gate of the MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET's input capacitance.
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FN6703.1 September 11, 2008
ISL6745A Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -B12 TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE -CL L1 4X R1 R 0.20 (0.008) ABC E
INCHES SYMBOL A A1 A2 b c D
4X
MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 4.75 0.40 10 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 0 12/02
MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 0.187 0.016 10 0.003 0.003 5o 0o
MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120 0.199 0.028
INDEX AREA
E1 e E L L1 N R R1
-B-
A
A2
0.020 BSC
0.50 BSC
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
SIDE VIEW
15o 6o
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN6703.1 September 11, 2008

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